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| ST1331D, ST1333D ST1353D 6-Contact Memory Card IC 272-bit EEPROM With Advanced Security Mechanisms and Inlock System DATA BRIEFING s s s s s s s s s s 5 V Single Supply Voltage Counting Capability (two options) - up to 32767 (85 -1) - 8 times reloadable, up to 4095 (84-1) Active Authentication Function (ST1333D/53D) Cipher Block Chaining Function (ST1353D) Memory Divided into : - 16 bits of Circuit Identification - 48 bits of Card Identification - 40 bits of Count Data - 16 bits for Validation Certificate - 24 bits of Transport Code - 64 bits of Issuer Data (ST1331D) or Authentication Secret Key (ST1333D/53D) - 32 bits of Anti-tearing Flags (optional) - 56 bits of User data (optionally not erasable) More than 500,000 Erase/Write Cycles More than 10 Years Data Retention 3.5 ms Programming Time at 5 V (typical) 500 A Supply Current at 5 V (typical) 250 A Stand-by Current at 5 V (typical) 1 Micromodule (D10) 1 1 1 Wafer DESCRIPTION The members of the ST1331D/33D/53D family are principally designed for use in prepaid Phonecard applications. Each is a 272-bit EEPROM device, with associated security logic and special fuses to control memory access. The memory is arranged as a matrix of 34 x 8 cells, accessed in a serial bitwise fashion for reading and programming, and in Figure 1. Logic Diagram VCC RST Table 1. Signal Names CLK RST B I/O VCC GND Clock Function Code Function Code Serial Data Input / Output Supply Voltage Ground B ST1331D ST1333D ST1353D I/O CLK GND AI03726 October 2000 Complete data available under NDA. 1/3 ST1331D, ST1333D, ST1353D Figure 2. D10 Contact Connections ST1331D ST1333D ST1353D VCC RST GND The anti-tearing mechanism guards against miscounts occurring when the card is prematurely extracted, while an operation is underway, in an open reader. MODES The device works in two distinct modes of operation: - Issuer Mode: for the card manufacturer. allowing custom data to be written to the device, to initialize it before release to the end user. - User Mode: for the end user of the card, with restricted, and controlled access to the device. Before delivery, from ST to the card issuer, the device is placed in the Issuer Mode. This operation is performed by blowing the "test fuse". OPTIONS Three options are available when ordering the device: - The anti-tearing mechanism can be disconnected. In this case, the anti-tearing flag area from bit 288d to bit 319d is unused (Figure 3). - The user area, from bit 320d to bit 375d, can be defined as "not erasable" in the User Mode. - The reload mechanism can be activated. In this case, erasing a bit in the reload counter refreshes the certificate (CER). At this time, the certificate can be programmed with a new value. ORDERING INFORMATION The notation used for the device number is as shown in Table 10. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office. CLK B Ai03107 I/O a byte-wise fashion for internal erasing. An on-chip address counter provides an internal address space of up to 512 bits. Each member of the ST1331D/33D/53D family has an identification data area, unit-counters (with an anti-tearing mechanism for reliable usage in open readers), a post validation certificate, an issuer area (ST1331D) or an authentication secret key area (ST1333D/53D), and a user area. This is summarized in Figure 3. The validation certificate allows the recognition of the device by the appropriate security module. When the 8 times reloadable option is activated, the certificate and the reload counter (address 64d to 71d) can be used to allow the recognition of the circuit by the appropriate security module. This will allow the development of a reloadable card as the certificate value is refreshed each time the reload counter is incremented. Table 2. Ordering Information Scheme Example: ST1333 D W4 / XX YY Product 33 31 53 Active Authentication Function Issuer Area Cipher Block Chaining Authentication Function Transport Code Given by ST Customer Code Given by the Issuer Revision D 5 V supply voltage, fuse blow and Inlock system D10 W4 Delivery Form Micromodule on reel Wafer (180 m thickness) Note: 1. Please contact your nearest ST Sales Office to check on availability 2/3 ST1331D, ST1333D, ST1353D Figure 3. Memory Map 0 16 Physical EEPROM Cells 32 bits 0 16 masked bits Circuit Identification Area Card Identification Area (ID) RAM1 (Write-Only) (RN) (ST1333D, ST1353D) 32 48 bits Data Area (CD) 40 bits 8 bits 16 bits (Counters and Transport Code) Reserved Area (RA) Certificate (CER) Issuer-Defined Area (ST1331D) 64 bits Authentication Secret Key (SK) (ST1333D, ST1353D) 64 104 112 128 Physical EEPROM Cells 192 64 bits Reserved Area (RA) 4 bits 4 bits 24 bits Signature Fuses Unused 256 260 264 288 Physical EEPROM Cells 32 bits Anti-Tearing Flags 320 56 bits User-Defined Area 376 AI03384B Note: 1. The write-only RAM area (RN) is applicable only for the User Mode. 3/3 |
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